The present invention relates in general to the domain of digital transmission techniques and more particularly to the domain of reception of a modulated signal transmitted through a cabled network.
One aspect of the present invention relates to a demodulation device comprising an input having a first power control circuit to maintain a constant amplitude of a modulated input signal in the presence of slow fluctuations in the amplitude of the carrier, with the modulated signal being transmitted to a set of demodulation circuits in series, on the output side of the first power control circuit, to apply a demodulation processing to the input signal.
The present invention is particularly suited for use in cabled networks in which transmitted signals are adapted to the ITU-J83 standards Annex A/B/C (“ITU” standing for “International Telecommunication Union”). Typically in this context, the transmitted signals are amplitude and phase modulated according to the QAM (Quadrature Amplitude Modulation) modulation technique.
FIG. 1 shows a system for reception of a modulated signal transmitted on a cable. This type of reception system is generally composed of the following blocks: a channels selector device TUNER, a demodulation device DEMOD, an error correction circuit FEC with no return channel and, connected to the output of the error correction circuit, a BACK_END processing circuit that depends on the type of data transmitted on the channel (for example, an MPEG decoder).
The channel selector device TUNER transposes the radio frequency analog signal, for example within the 48–900 MHz range, to an intermediate frequency analog signal, for example 36, 44 or 57 MHz, that the demodulator can use. The demodulator device estimates the symbols sent. In other words, it eliminates the modulation to enable the change from the intermediate frequency analog signal to a base band digital signal sampled at the data transmission speed. The error correction circuit FEC with no return channel uses error correction decoding. Therefore it corrects the error and eliminates the redundancy introduced into the signal by the encoder present in the modulation circuit. The output from the error correction circuit FEC is then composed of packets of bytes organized in the form of frames, called Transport Streams (TS), with a defined format and comprising synchronization data in addition to the transported data.
The demodulation device in the reception system is conventionally composed of the demodulation circuits described in FIG. 2. An Automatic Gain Control (AGC) circuit is built into the input of the demodulation stage so as to keep the average level of the useful signal approximately constant before demodulation. This circuit advantageously makes a measurement of the power of the signal at the input to the reception device, and through a counter reaction loop, acts on the amplification of the input stages so as to keep the amplitude of the output signal constant in the presence of slow fluctuations of the carrier.
The demodulation device also comprises two synchronization loops. A first loop, called the timing loop TL, is designed to estimate and correct the error between data sending frequencies and the data reception frequency (for example, these frequencies are on the order of 5 MHz for the ITU A/B/C standards). The second loop, called the carrier loop CL, is designed to estimate and correct the error between data modulation and demodulation frequencies (this frequency is conventionally equal to 36, 44 or 57 MHz at the demodulator input).
An equalizer circuit EQU is also incorporated to estimate and correct linearity defects present in the transmission system. It also cancels out the different signal echoes. The equalizing circuit is conventionally composed of one or several adaptive filters.
Such demodulation circuits of the demodulator and FEC assembly are actually clocked at the rate of a clock frequency FClk, by elementary sequential elements. The clock frequency is usually greater than the data frequency and the rate of operations is usually controlled by a synchronization signal samp_en emitted through a control circuit CTRLC. When the samp_en signal is at logical level 1, the operation is performed. When it is at logical level 0, the operation is not performed. During normal operation, the samp_en signal is a periodic clock signal with a frequency proportional to the data reception frequency.
The following briefly describes the main operating steps used during reception of a channel by the reception system. Conventionally, the reception system operates in two modes: an acquisition mode and a “tracking” synchronization mode.
After the desired channel has been selected, the reception system is programmed in acquisition mode. In this mode, only the demodulation device DEMOD and the error correction circuit FEC are used. In acquisition mode, the automatic gain control AGC circuit of the demodulator begins by controlling the input power. When the power has been adjusted to its nominal level, the two synchronization loops TL and CL and the demodulator stage equalizer EQU are started. After convergence of the synchronization and equalizer loops, the demodulator changes to tracking mode.
In tracking mode, the demodulator follows and compensates for the slow variations in the characteristics of the signal received through the automatic gain control AGC circuit, the synchronization loops TL and CL and the equalizer EQU. Starting from this moment, the data output from the demodulator to the FEC circuit can be used. The FEC circuit then changes to acquisition mode.
After synchronization of the FEC, the transport stream TS at the output of the FEC circuit has the right frame structure and the BACK_END processing circuit can then be started in turn.
The time between selection of the required channel and synchronization of the transport stream TS at the output of the demodulator and FEC assembly is called TSyncDemodFEC and is on the order of 100 ms.TSyncDemodFEC=TSyncDemod+TSyncFECwhere TsyncDemod is the demodulator synchronization time that is on the order of 80 ms and TSyncFEC is the synchronization time of the FEC circuit that is on the order of 20 ms.
The time necessary between synchronization of the FEC circuit and synchronization of the processing circuit is called TSyncBackEnd and is on the order of 500 ms.
Thus, a time “TSyncDemodFEC+TSyncBackEnd”, which is on the order of 600 ms, is necessary between the time that the channel is selected and synchronization of the processing circuit.
Many physical phenomena can cause transmission “holes” that normally result in short interruptions to signal reception by the demodulator. A typical case of short interruptions to signal reception is disconnecting and then reconnecting the reception cable.
Thus, when the reception cable is accidentally disconnected and then reconnected, the signal disappears for a short moment. However, this short disappearance of the signal causes loss of synchronization of the demodulator device, and in particular causes desynchronization of the timing and carrier loops and divergence of the equalizer. The demodulator is therefore desynchronized and the result is desynchronization of the FEC circuit and the BACK_END processing circuit.
One current solution to overcome this problem is to detect the loss of synchronization of circuits in the reception device, and then reprogram the demodulator and FEC assembly in acquisition mode and wait for these circuits to be resynchronized. In particular, detection of loss of synchronization normally is done by detecting that the transport stream TS at the output of the FEC circuit is corrupted, or that the data at the output of the BACK-END circuit is corrupted. In this case, the demodulator changes back to acquisition mode. Reception is then interrupted for a time defined as follows.Tinterruption+TDetect+TSyncDemod+TSyncFEC+TSyncBackEndwhere TDetect is the time to detect the loss of synchronization of the output of the FEC circuit (or at the output of the BACK_END circuit) and Tinterruption is the time of interrupted communication on the cable.
Therefore, due to the time necessary to resynchronize the different reception circuits, and particularly the demodulator circuit, the reception interruption time is a major disadvantage when the signal accidentally disappears for a short moment.
Moreover, this problem requires action by the software controlling the different operating modes of the reception system since the demodulator and FEC assembly have to be reprogrammed in acquisition mode so that these circuits can be resynchronized following a short disappearance of the signal. The processing unit of the reception system using the control software is therefore permanently busy throughout the duration of the channel reception process to ensure that operations take place correctly and to take action if the signal disappears at the input to the demodulator for a short instant, and consequently its resources cannot be released for other purposes.